Algorithmic Memory Technology Overview

Breakthrough Memory Performance

Memory performance continues to be outpaced by the ever increasing demands of faster processors, multiprocessor cores and parallel architectures. In particular, embedded memory performance has become the limiting factor in overall system performance for SoC designs. Circuit techniques and advances in lithography alone can no longer provide the needed embedded memory performance. In addition, SoC designs need memories that are area efficient and consume less power.

To address the above needs, Memoir has pioneered a completely new solution – Algorithmic Memory™, which uses the power of algorithms to increase the performance of existing embedded memory macros – up to 10X more Memory Operations Per Second (MOPS), and lowers area and power consumption.

Memory Bandwidth versus MOPS

Memory bandwidth is the rate at which data can be read from or stored into a memory. It is a measure of the rate of data transfer from memory, and can be increased by expanding the data bus width of the memory. This increases performance but does not allow more accesses to the memory (on the address bus). A distinct and more inclusive measure of memory performance is MOPS, which refers to the rate at which unique accesses can be performed to memory. Doubling MOPS, doubles the number of accesses supported by the memory, and as a consequence also doubles the total memory bandwidth. The use of MOPS to measure memory performance is analogous to the use of IOPS (Input/Output Operations Per Second) to benchmark computer storage devices such as hard disk drives, solid state drives.

How does Algorithmic Memory work?

Memoir’s algorithms increase the performance of existing memory macros by implementing a variety of techniques such as caching, virtualization, pipelining, and data encoding; then weaving them together to operate seamlessly. The internals of these techniques are transparent and the result is an Algorithmic Memory, which presents multiple memory interfaces that can all be accessed simultaneously, giving significantly more MOPS. The performance is increased in a completely predictable manner with no exceptions whatsoever, even resolving all traditional row, address, and bank conflicts that may arise due to simultaneous accesses from the multiple interfaces. This means that the performance is guaranteed irrespective of the sequence of simultaneous address accesses and data patterns. This performance guarantee has been mathematically proven using adversarial analysis models. Moreover, each implementation of Algorithmic Memory is formally verified.

Algorithmic Memory Diagram


How is Algorithmic Memory configured?

Memoir’s Algorithmic Memory allows memory performance to be viewed as a configurable resource. System architects and designers need only specify (with a simple push button interface) the characteristics of their desired memory, i.e. the number of read and write interfaces, the clock frequency to operate, and any special requirements with regard to area and power optimizations. With this information, Memoir is able to take an existing standard memory library, incorporate its memory algorithms, and synthesize a new memory customized for the user’s requirement.

Additional information